Tunnelling Static Random Access Memories

One of the main problems in present microprocessors is that static power dissipation in six transistor SRAM is now comparable to the dynamic power dissipation and so chips now require sophisticated power management systems to allow the chip to function. If a lower power technology could be found this would have major implications for sub-100 nm CMOS microprocessors. One potential technology is the Tunnelling Static Random Access Memory (TSRAM) shown below which is predicted to have seven orders of magnitude lower power dissipation an present six transistor CMOS memory.

The operation requires two RTDs integrated with a MOSFET which forms two stable points on the load line plot that can be used as the 1 and 0 states.

The TSRAM allows RTDs to be easily integrated when strained-Si transistors on a relaxed Si0.8Ge0.2 virtual substrate as shown on the right to provide a compact memory with long retention time, access times comparable to six transistor CMOS SRAM and static power dissipation which is seven orders of magnitude lower than conventional six transistor SRAM (see table below).