Dr. Xingsheng Wang

Welcome to the webpage of Dr. Xingsheng Wang (Chinese name 王兴晟).

Xingsheng Wang received the academic training from several disciplines. He obtained the Ph.D. degree in electronics and electrical engineering from University of Glasgow in July of 2010. His Ph.D. study presented a comprehensive bulk MOSFET scaling projection of device design and statistical variability subject to realistic structures starting from 45nm CMOS technology. His Ph.D. study was under the supervisions of Prof. Asen Asenov and Prof. Scott Roy, and with the full support of UK EPSRC studentship and ORS awards scheme. He acquired MPhil degree in mathematics from Tsinghua University with top prize in January 2007. His master research in mathematics covered analysis on fractals under the directions of Prof. Jiaxin Hu. He had B.S. degree in electronic science and technology from Beijing Technology and Business University with top prize in 2004, focusing on signal processing and telecommunication systems.

He was a Research Associate with Device Modelling Group in the School of Engineering at University of Glasgow until 2016. His research interest involves nanoscale MOSFET devices, TCAD and atomistic modeling and numerical simulations, and intrinsic parameter fluctuations due to statistical variability and reliability. The modelling and simulation tools include TCAD suite Sentaurus and the Glasgow 'atomistic' simulator for process and device simulations, and BSIM4, BSIM-CMG, BSIM-IMG, UTSOI2 etc. for compact modelling, and SPICE-like simulators. For the first time, he has successfully developed the hierarchial compact model approach and explored novel methodologies of variability-aware design technology co-optimization (DTCO) of nanoscale technologies in the world, which later are adopted by EDA companies.

He has participated in a series of research projects, including, EU Horizon 2020 project "Revolutionary embedded memory for internet of things devices and energy reduction (REMINDER)"(Administration, 2016.1-); FP7 ICT project "Circuit stability under process variability and Electro-Thermal-Mechanical coupling (SUPERTHEME)"(2013-2015.12); Scottish Funding Council project "Statistical Design and Verification of Analogue Systems (StatDes)" (2012-2013); EU ENIAC joint undertaking project "MOdeling and DEsign of Reliable, process variation-aware Nanoelectronic devices, circuits and systems (MODERN)"(2010-2012); EU FP7 project "Terascale reliable adaptive memory systems (TRAMS);" UK EPSRC project "Meeting the design challenges of nano-CMOS Electronics."

PhD Thesis: "Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs," University of Glasgow, 2010.

He has published around 20 papers in IEEE TED, IEEE EDL and APL etc. featuring two cover story (invited) papers in IEEE TED, and more than 40 papers in well-known conferences with several (invited) IEDM, VLSI-Tech papers, during his period at University of Glasgow.

In May 2016, Dr. Wang left the University of Glasgow and joined Synopsys.

Research fields & Publication list.

Selected Publications

  • An VLSI-Tech. paper on nanowire DTCO is accepted in 2016.
  • An ISQED paper on nanowire DTCO for 5nm and beyond is invited in 2016.
  • An IEEE TED paper on 14nm FinFET hierarchical variability-aware compact modelling mothodology is accepted in July 2015.
  • An IEEE TED paper on the quantum confinement impact on nanowire transistors is accepted in August 2015.
  • An IEDM paper on the predictive compact modeling of FinFET variations is accepted in August 2015.

  • A. Asenov, B. Cheng, X. Wang, A. R. Brown, C. Millar, C. Alexander, S.M. Amoroso, J. B. Kuang, S. Nassif, "Variability aware simulation based design-technology cooptimization (DTCO) flow in 14 nm FinFET/SRAM cooptimization," IEEE Transactions on Electron Devices, Vol.62 No.6, pp.1682-1690, June 2015. (Invited Paper. Cover story)
  • X. Wang, A. R. Brown, B. Cheng, S. Roy and A. Asenov, "Drain bias effects on statistical variability and reliability and related subthreshold variability in 20-nm bulk planar MOSFETs," Solid-State Electronics, Vol.98, pp.99-105, Aug. 2014.
  • X. Wang, B. Cheng, A. R. Brown, C. Millar, J. B. Kuang, S. Nassif, and A. Asenov, "Statistical variability and reliability and the impact on corresponding 6T-SRAM cell design for a 14-nm node SOI FinFET technology," IEEE Design & Test, Vol.30 No.6, pp.18-28, December 2013.
  • A. Asenov, B. Cheng, X. Wang, A. R. Brown, D. Reid, C. Millar, C. Alexander, "Simulation based transistor-SRAM co-design in the presence of statistical variability and reliability," in Proc. IEEE International Electron Devices Meeting (IEDM), Washington DC, 9-11 Dec. 2013, pp.818-821. (Invited paper)
  • X. Wang, B. Cheng, A. R. Brown, C. Millar, C. L. Alexander, D. Reid, J. B. Kuang, S. Nassif, and A. Asenov, "Unified compcat modelling strategies for process and statistical variability in 14-nm node DG FinFETs," in Proc. SISPAD, Glasgow UK, Sept. 2013, pp.139-142. [PDF], [Slides]
  • X. Wang, B. Cheng, A. R. Brown, C. Millar, J. B. Kuang, S. Nassif, and A. Asenov, "Interplay between process-induced and statistical variability in 14-nm CMOS technology double-gate SOI FinFETs," IEEE Transactions on Electron Devices, Vol.60 No.8, pp.2485-2492, August 2013.
  • X. Wang, A.R. Brown, B. Cheng and A. Asenov, "RTS amplitude distribution in 20nm SOI finFETs subject to statistical variability," in Proc. SISPAD, Denver CO, Sept. 5-7, 2012, pp.296-299.
  • X. Wang, F. Adamu-Lema, B. Cheng, and A. Asenov, "Geometry, Temperature, Body Bias Dependence of Statistical Variability in 22-nm bulk CMOS technology: a comprehensive simulation analysis," IEEE Transactions on Electron Devices, Vol.60 No.5, pp.1547-1554, May 2013.
  • X. Wang, G. Roy, O. Saxod, A. Bajolet, A. Juge, and A. Asenov, "Simulation study of dominant statistical variability sources in 32-nm high-k/metal gate CMOS," IEEE Electron Device Letters, Vol.33 No.5, pp.643-645, May 2012.
  • X. Wang, A.R. Brown, B. Cheng and A. Asenov, "Statistical Variability and Reliability in Nanoscale FinFETs," in Proc. IEEE International Electron Devices Meeting (IEDM), Washington D.C., December 5-7, 2011, pp.103-106. [Slides]
  • X. Wang, A.R. Brown, N. Idris, S. Markov, G. Roy and A. Asenov, "Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study," IEEE Transactions on Electron Devices, Vol. 58, No. 8, pp. 2293–2301, Aug. 2011. (Cover Story)
  • X. Wang, S. Roy, A.R. Brown and A. Asenov, "Impact of STI on Statistical Variability and Reliability of Decananometer MOSFETs," IEEE Electron Device Letters, Vol. 32, No. 4, pp. 479–481, Apr. 2011.

English CV, Chinese CV

PhD graduation link (Morning 1st July), Master graduation link

Erdös number = 4

New version personal webpage


School of Engineering
University of Glasgow
Rankine Building, Oakfield Avenue
Glasgow G12 8LT, Scotland U.K.
Email: Xingsheng.Wang at glasgow dot ac dot uk
Telephone: +44(0)141 330 2964

[forward] Last updated on 19th August 2013.
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