Simulation of noise in nano-CMOS devices
Background
As the channel length of mass produced MOSFETs continues to shrink, their low frequency noise becomes a significant factor in analogue circuit performance [1], memory operation [2], and will eventually impact upon the reliability of digital logic. Random telegraph signals (RTS) resulting from the capture and emission of charge from defect states near the Si/SiO2 interface dominate the low frequency noise performance of small MOSFETs around and below threshold [3], and RTS amplitudes larger than 60% have been reported [4]. Other effects which are of concern as device dimensions shrink, are those arising from the granularity of charge and matter, as described in our work on the Simulation of intrinsic parameter fluctuations in nano-CMOS devices. We are particularly interested in the consequences of such 'atomistic' effects on the RTS noise in a single decanano device, or ensembles of decanano devices.
Methodology
Our approach [5] uses a 3D drift-diffusion simulator which describes the electrostatic effects associated with random discrete dopants, and can accurately calculate RTS in the sub-threshold regime. For low drain voltages (VD = 10 mV allows us to remain within the regime of applicability of the simulator) and devices of 30×30 nm with a smooth nominal doping, the drain current may drop by up to 40% on activation of a trap. Fig. 1 plots the potential across one of these devices, clearly showing the potential barrier of the channel in sub-threshold, and indicating how that barrier is augmented by trap activation. It is clear that if the trap is found nearer to the source or drain junction its effect on sub-threshold current will be markedly reduced, either because in the source/drain depletion regions the trap is no longer at the peak of the potential barrier, or because further into the source/drain regions it is heavily screened. In addition, a trap found offset from the centre of the channel width will leave the opposite region of the channel augmented by a lower Coulomb field. These results are shown quantitatively in Fig 3, which maps the fractional RTS magnitude as a function of trap position in a non 'atomistic' channel.
 |
 |
|
| (a) | (b) | |
| Fig. 1 RTS amplitudes in ideal, continuously doped ultrasmall MOSFETs: (a) Potential barrier between source and drain in a 30×30 nm MOSFET showing the effect of a single unscreened trapped charge at the interface. (b) Positional dependence of the magnitude of RTS fluctuations in the drain current of a 30×30 nm MOSFET with an assumed continuous spread of doping, as a function of trap position in the channel region. | ||
An advantage of our 3D approach is that RTS amplitudes can be obtained in the presence of the fluctuating channel potentials found in realistic MOSFETs subject to discrete random dopants. Fig. 4 shows three different discrete profiles (ordered by increasing threshold voltage from left to right) for 30×30 nm devices, and the positional dependence of RTS amplitude in each configuration. In the middle plot, most of the dopants within 3 nm of the Si/SiO2 interface are found to be to the 'north' side of the channel, raising the potential in this area. For any given gate voltage, current will flow most easily from source to drain along the lower potential 'southern' region of the channel. Trap activation in this region will have greatest effect on the overall current flow. In the left hand plot most dopants are again found to the 'north' of the channel, with one additional dopant in the 'south' producing a narrow percolation path. Trap activation in this path gives RTS amplitudes of up to 70%. In the right hand plot, in addition to a higher dopant density near the Si/SiO2 interface raising VT, the dopants are more uniformly distributed across the width of the channel, and the positional dependence of the RTS fluctuations more closely approaches that of a continuously doped device.
 |
| Fig. 2. Positional dependence of the magnitude of RTS fluctuations in drain current caused by a single trap/de-trap event in one of three 30×30 nm MOSFETs subject to discrete random dopants in the channel region. Dopant position saturation indicates whether these dopants fall within the 1st, 2nd or 3rd nm from the Si/SiO2 interface. |
Although a particular atomistic device may exhibit RTS amplitudes over 70%, approaching twice that of devices with a nominally continuous dopant spread, the ensemble average has approximately the same peak value as that of a continuous device. However the formation of percolation paths in the presence of atomicity means that trap activation at any point along the width of the channel may produce strong fractional RTS amplitudes, a distinct feature resulting from the consideration of more realistic devices.
Time and frequency domain simulation
 |
| Fig. 4. Methodology overview for extracting time domain results from 'atomistic' device simulations (where RTS amplitudes may be obtained as a function of trap position and trap/de-trap statistics can be calculated as a function of trap energy level and electron density). |
Having calculated the distribution of the RTS amplitudes, the simulator may be extended to obtain time domain results (and hence power spectral densities of noise in ultra-small MOSFETs in the sub-threshold regime) once statistics of the thermally activated trap capture and emission times are known.
The methodology is overviewed in Fig. 6. The top graph shows the probability of a given RTS amplitude in an ensemble of 30×30 nm MOSFETs. The right hand cartoon indicates the introduction of specific trap/de-trap timing by Monte Carlo. The lower graph is part of a typical simulation combining both amplitude and timing. It is a small segment taken from one member of the ensemble near threshold at low drain voltage, VG = 0.5 V, VD = 0.01 V, and clearly indicates the effect of two active traps in the device. From the full trace – in this case over a simulation time period of > 400 s – a power spectral density may be obtained.
Conclusions
We are developing a methodology and corresponding simulation tools to model both the magnitude and timing of RTS noise in decanano MOSFETs subject to atomic scale variations in dopant positions The approach, illustrated simulating noise in 30×30 nm devices, can be extended to a wide variety of device architectures from present devices, down to the end of the roadmap.
REFERENCES:
[1][2]
[3]
[4]
[5]