Background

Progressive scaling of CMOS transistors has driven the phenomenal success of the semiconductor industry, delivering faster, cheaper circuits with ever increasing functionality. Silicon technology has now entered the nano-CMOS era with 40 nm MOSFETs in mass production at the current 90 nm technology node [1] and sub-10 nm transistors expected to be in production by 2018 [2] - although the classic MOSFET architecture is likely to be surpassed by ultra-thin-body SOI or FinFET technologies [3]. However, it is widely recognised that variability in device characteristics represent a major challenge to the scaling and integration of both present and next generation nano-CMOS transistors and circuits, as described in our work on the Simulation of intrinsic parameter fluctuations in nano-CMOS devices

This variation will be one of the drivers of revolutionary changes in the way in which future integrated circuits and systems are designed. For example the illustration below shows that for 35 nm gate length MOSFETs, traditionally designed SRAM will fail to meet the required noise margins for acceptable chip yield, due to intrinsic parameter fluctuations. To obtain the yield necessary, the cell ratio (and thus the silicon area of each cell) must be increased, negating the scaling advantage of moving to a 35 nm process. New circuit design techniques, informed by fluctuation analysis, are needed to give the continued systems improvements predicted in the ITRS.

(a)	(b)	(c)
Fig. 1 The problem of intrinsic parameter fluctuations. (a) 3D simulation of potential in a 35×35 nm MOSFET featuring random discrete dopants. Channel potential variations due to different dopant configurations give different I–V characteristics from device to device. (b) I–V characteristics of an ensemble of 200 such devices clearly showing variations in off- and on-current. (c) Calculated distribution of noise margins in SRAM cells constructed from members of the ensemble of MOSFETs. Some SRAMs with cell ratio = 1 have zero noise margin and never operate correctly. Only SRAMs with cell ratio >3 have sufficient noise margin to give 90% yield in 1Mbit memories under normal operating conditions.

Variations caused by intrinsic parameter fluctuations are more complex than traditional process variation (for example, the granularity of MOSFET channel doping will be important in sub-threshold, but less important in saturation due to increased screening [4]). Traditional worst-case simulation, ignoring the detailed statistics of these fluctuation distributions may invoke unnecessarily tight process controls and fabrication costs, or unneeded delay in the jump to a new technology node. Therefore our research is aimed at developing tools and methodologies which allow transfer of parameter fluctuation information from experiment or physical simulation of realistic devices down to the 22 nm technology node, coping with a range of architectures, materials, and scales – to industry standard EDA tools. This will allow circuit and system designers to assess both qualitatively and quantitatively the impact of intrinsic parameter fluctuations on circuit operation, and to design defensively where necessary.

Methodology

Our present research is based on an optimised methodology for extracting an ensemble of compact model parameters from statistical data produced by either experiment or device simulation. These compact model parameters (we have used BSIM3v3, BSIM4 and BSIMSOI, and are investigating surface potential models) are then used to perform statistical SPICE circuit simulation of the foundational building blocks in both analogue and digital circuit design. Whilst a typical compact model might contain tens of parameters, fluctuation effects can be adequately captured with a small subset (5 or 6) of these parameters, with all the others remaining fixed over the device ensemble.

Fig. 2. Three BSIM3 compact model parameters strongly dependant on intrinsic parameter fluctuations, and their statistical spread over 100 35×35 nm devices. Voff is one of the controls over sub-threshold slope, Nch describes the effective channel doping, and a0 directly affects the drain saturation voltage.

Circuit Design

We have investigated the operation of a number of different analogue and digital circuits under the influence of intrinsic parameter fluctuations, including ring oscillators and cascode current mirrors [5], low swing driver circuitry [6], and a range of digital logic styles including CMOS, pass transistor logics, Domino logic and differential cascode voltage switch (DDCVS) logic [7]. Intrinsic parameter fluctuations have been found to profoundly affect analogue circuit matching and the power consumption, yield and reliability of digital circuits.

One important and instructive example is SRAM, which occupies significant real estate in current Systems On Chip (SoC) and microprocessors, and is notoriously sensitive to parameter fluctuations due to its highly constrained cell size. Fig. 3 shows the circuit diagram of an SRAM cell and defines the two most important noise margins involved in its operation. The stability of an SRAM cell is usually associated with the SNM, and as Figs. 4(a) and 4(b) show, stability in the presence of intrinsic parameter fluctuations is most sensitive to SNM. With 35×35 nm devices of equal width (cell ratio 1.0) SNM is so highly degraded that any system containing SRAM will have negligible yield. Even at a cell ratio of 2.0, SNM is small enough that yield would be considerably less than 90% on 1Mbit SRAM memory. The most effective way to improve SRAM yield is to improve the SNM performance, and traditionally this has been done by increasing the cell ratio. Without considering more subtle design trade-offs, SRAM cell area will therefore not be able to decrease proportionately with technology node, and SRAM will not secure the major benefits of conventional CMOS scaling.

Our analysis methodology, however, suggests another solution to the problem. The effect of intrinsic parameter fluctuations on WNM values is not critical. If the SRAM access transistors were weakened (say by local changes in threshold voltage or back bias) the SNM would increase and the WNM decrease - but as long as the WNM does not decrease enough to become the dominant factor, overall device stability is improved. Fig 4(c) shows the result of weakening the access transistors by 20%. In this case the yield on 1MBit SRAMs is increased to over 90%.

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Fig. 3 Transfer characteristics of SRAM cells. Showing (a) the circuit diagram of an SRAM cell (b) the definition of Static Noise Margin (the DC noise voltage required during a read period to obtain a the opposite value to the actual information stored in the cell) and (c) the definition of Write Noise Margin (the DC noise voltage needed to fail to flip a cell during a write period where the intention was to change the cell state).

(a)	(b)	(c)
Fig. 4 SRAM subject to intrinsic parameter fluctuations. (a) static transfer characteristics over an ensemble of 200 SRAM cells with cell ratio (ratio of current drive of driving transistors such as M2 to access transistors such as M5) equal to 1.0 (b) static transfer characteristics over and ensemble of 200 SRAM cells with the more normal cell ratio of 2.0, and a normal driveability ratio (ratio of current drive of access to load transistors) of 2.0 (c) effect on SNM and WNM distributions of lowering the driveability ratio whilst keeping the cell ratio constant - the critical SNM improves, whilst the less worrisome WNM is degraded.

Systems Design

Fig. 6. Hierarchical simulation methodology needed to capture the impact of variability on design.

Strong links must be established between circuit design, system design and fundamental device technology to allow circuits and systems to accommodate the individual behaviour of every transistor on a chip. Design paradigms must change to accommodate this increasing variability. Adjusting for new device architectures and device variability will add significant complexity to the design process, requiring orchestration of a broad spectrum of design tools by geographically distributed teams of device experts, circuit and system designers. This can only be achieved by embedding e-science technology and know-how across the whole nano-CMOS electronics design process and revolutionising the way in which these disparate groups currently work.

Solutions to these problems are the focus of a new EPSRC grant, led by us, and consisting of University partners including the Device Modelling and Microsystems Technology groups at Glasgow, the Advanced Processor Technologies group at Manchester, the Electronic Systems Design group at Southampton, the Intelligent Systems group at York, and the Mixed-mode Design group at Edinburgh. e-Science and Grid technologies built to enable these groups to work in novel and productive ways are being develops in collaboration with the National e-Science Centre, and e-Science North-West Centre. Industrial support is provided by ARM, Wolfson Microelectronics, Synopsys, Freescale, National Semiconductor, Fujitsu, and the National Microelectronics Institute.

The aims of this upcoming work are to:

• understand and forecast the behaviour of next generation nano-CMOS devices using Grid-enabled simulations;
• develop strategies to capture new device characteristics and variability, enabling more efficient circuit design;
• develop hybrid, Grid based device/circuit/system simulation techniques;
• investigate the impact of new device architectures and device variability on established design components;
• develop novel design concepts;
• learn how researchers can use e-science technologies to enable them to undertake research hitherto impossible.