Introduction

In the past couple of years MOSFETs have reached decananometre (between 10 nm and 100 nm) dimensions with 40-50 nm physical gate length devices available now in the 90 nm technology node, 35 nm transistors ready for mass production in 2-3 years time and 15 nm, and even 10 nm, MOSFETs with conventional architecture demonstrated in a research environment. The 2001 edition of the International Technology Roadmap for Semiconductors forecasts that the MOSFET will become a nanometre scale (i.e. sub-10nm) device after 2016 when its physical dimensions in a mass production environment will reach 9 nm.

(a)	(b)	(c)
Fig. 1 Transition from continuous towards ‘atomistic’ device concepts: (a) The traditional approach to semiconductor device simulation assumes continuous ionised dopant charge and smooth boundaries and interfaces; (b) Sketch of a 20 nm MOSFET expected in mass production before 2010. There are less than 50 Si atoms along the channel. Random discrete dopants, atomic scale interface roughness, and line edge roughness introduce significant intrinsic parameter fluctuations; (c) Sketch of a 4 nm MOSFET expected in mass production in 2020. There are less than 10 Si atoms along the channel. The device becomes smaller than biologically important molecules such as ionic channels.

Figure 1 shows that MOSFETs are becoming truly atomistic devices. The conventional way of describing, designing, modelling and simulating such semiconductor device, illustrated in Fig. 1a, assuming continuous ionised dopant charge and smooth boundaries and interfaces, is no longer valid. The granularity of the electric charge and the atomicity of matter, as illustrated in Fig. 1b, begin to introduce substantial variation in individual device characteristics. The variation in number and position of dopant atoms in the active region of decananometre MOSFETs makes each transistor microscopically different and already introduces significant variations from device to device. In addition, the gate oxide thickness becomes equivalent to several atomic layers with a typical interface roughness of the order of 1-2 atomic layers. This will introduce a variation in the oxide thickness within an individual transistor of more than 50%, resulting in each transistor having a microscopically different oxide thickness pattern. The unique oxide roughness pattern in each decananometre MOSFET will affect the device electrostatics, the surface roughness limited mobility and the gate tunnelling from device to device. The granularity of the gate material and the photoresist, together with other factors, will introduce unavoidable line edge roughness (LER) in the gate pattern definition and statistical variations in geometry between devices. When combined together the variations in dopant statistics, oxide thickness pattern, gate material and geometry will have a crucial impact on the functionality, yield and reliability of the corresponding circuits and systems at a time when the fluctuation margins shrink due to continuous reduction in supply voltage and increased transistor count per chip. As it has been shown in the past such fluctuations might affect not only analogue circuits but also the yield and functionality of the corresponding digital circuits. For example, in a ten billion transistors chip at least 20 transistors are expected to have a 6σ deviation in their parameters, assuming gaussian statistics. With 0.85 V supply voltage and expected threshold voltage standard deviation σV_T in the range of 20 - 30 mV there will be at least 20 transistors with threshold voltage of zero or half the supply voltage.

The sub 10 nm MOSFET illustrated in Fig. 1c is essentially a molecular scale device. It is anticipated, however, that the scaling of the field effect transistor below the 10 nm barrier requires an intolerably thin gate oxide and unacceptably high channel doping, and therefore demands a departure from the conventional MOSFET concepts. One of the most promising new device structures, scalable to dimensions below 10 nm, is the double gate MOSFET studied extensively in the last couple of years. To allow a full appreciation for the importance of the atomic scale effects in such devices we present in Fig. 2a, b respectively the atomic scale structure of a 10 nm and a 4 nm double gate MOSFET ‘fabricated’ using Photoshop and a real TEM image of the Si/SiO₂ interface.

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Fig. 2. Impression of (a) a 10 nm and (b) 4 nm gate length double gate MOSFETs based on a TEM image of the Si-SiO2 interface to illustrate the various sources of intrinsic parameter fluctuations.

Numerical simulation

The statistical variations in decananometre devices shift the paradigm of numerical device simulations. It is no longer sufficient to simulate a single device with continuous doping distribution, uniform oxide thickness and unified dimensions to represent one macroscopic design. Each device is microscopically different at the level of dopant distribution, oxide thickness and gate pattern, so an ensemble of macroscopically identical but microscopically different devices must be characterised. The aim of the numerical simulation shifts from predicting the characteristics of a single device towards estimating the mean values and the variance of basic design parameters, such as threshold voltage, subthreshold slope, transconductance, drive current, etc. for a whole ensemble of microscopically different devices in the system. It must be emphasised that even the mean values obtained from, for example, statistical atomistic simulations are not identical to the values corresponding to continuous charge simulation. The simulation of a single device with random dopants, oxide thickness and gate pattern variation requires a 3D solution with fine grain discretisation. The requirement for statistical simulations transforms the problem into a four-dimensional one where the fourth dimension is the size of the statistical sample.

Random Discrete Dopants

A typical atomistic solution domain used in the simulation of well scaled 35×35nm MOSFET is shown in Fig. 3a. The discrete dopants are placed in the active region of the device including the source and drain. In the rest of the simulation domain the doping charge has a continuous distribution to simplify the handling of the boundary conditions. In ohmic boundary conditions used at the contact region the doping concentration is used to define electro neutrality. This is how boundary conditions are imposed in traditional simulations. Numerical experiments show that only dopants which are adjacent to the active region of the device influence the fluctuations. Each and every silicon atom position in the simulated device is identified, and a random number is rolled to determine whether or not it is a dopant depending on the local continuous doping concentration. The potential distribution at a gate voltage equal to the threshold voltage is depicted in Fig. 3a and exhibits strong potential fluctuations at the Si-SiO₂ interface associated with the discrete dopants. One electron equi-concentration contour, which corresponds to this solution, is presented in Fig. 3b also showing the location of dopants.

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Fig. 3. Simulation domain in typical atomistic DG simulations of a 35×35nm MOSFET: (a) Potential distribution; (b) One equi-concentration contour and dopant positions (Red: Donors; Blue: Acceptors).

Numerical simulations have shown that the dopants closest to the interface are responsible for a large fraction of the intrinsic parameter fluctuations and this is confirmed by analytic work. Therefore devices with steep halo channel doping of low doped epitaxial channels show significant dopant fluctuation resistance. Double-gate devices do not require channel doping to operate and therefore are considered to be inherently resistant to random dopant induced parameter fluctuations. However when the double gate devices are scaled to dimensions below 10 nm (see for reference Fig. 2) the placement of random discrete dopants in the source/drain regions results in fluctuations in the effective channel length along the width of the device on a scale comparable to the average distance between the dopants. At typical source/drain doping concentrations in the range of 10²⁰ cm^-3 the average distance between the dopants is about 2 nm, constituting a large proportion of the channel length and becoming accountable for significant variations in the device parameters. The dependence of the standard deviation in threshold voltage, σV_T, as a function of channel length are shown in Fig. 4 for well scaled double gate MOSFETs. The magnitude of the fluctuations increases dramatically as the channel length reduces from 10 nm to 4 nm. For the 4 nm device the standard deviation in threshold voltage is approximately 70 mV. Assuming a ±3σ spread around the mean in a normal distribution of V_T this gives a range of approximately ±0.2 V around the nominal threshold voltage of V_T~0.2 V. This means that a significant number of the devices on a chip with a billion transistors will not turn off.

Fig. 4. Standard deviation in threshold voltage, σVT, due to random discrete dopants in the source and drain of double gate MOSFETs with different channel lengths.

Single Charge trapping

Trapping of a single carrier charge in defect states near the Si/SiO₂ interface, and the related local modulation in carrier density and/or mobility in an area comparable with the characteristic device dimensions, will have a profound effect on the drain and gate current in decananometre MOSFETs. Corresponding random telegraph signals (RTS) with amplitudes larger than 60% have already been reported at room temperature in decananometre channel width devices. Current fluctuations on such a scale will become a serious issue, not only as a source of excessive low frequency (LF) noise in analogue and mixed-mode circuits, but also in dynamic memories and possibly in digital applications. Depending on the device geometry a single or few discrete charges trapped in hot carrier or radiation created defect states will be sufficient to cause a pronounced degradation in decananometre MOSFETs. However, the modelling and simulation efforts are mainly restricted to simple analytical models and 2D numerical simulation studies and, for example, fall short of explaining the wide range of RTS amplitudes observed in otherwise identical devices. There are suggestions that strategically located traps influence the magnitude and the spreading of RTS amplitudes due to surface potential fluctuations and channel non-uniformity. However such potential fluctuations have been mainly associated with oxide non-uniformity and fixed and trapped interface charges. Only recently has the impact of the random discrete dopants been considered.

The atomistic simulation approach has been applied to study the impact of a single trapped charge on the current in decananometre MOSFETs when the random discrete dopant distribution in the channel is properly taken into account. The random dopant induced surface potential fluctuations result in current percolation through the ‘valleys’ in the potential landscape. These dominate the current flow, particularly in weak inversion where the ionised acceptor charges are not screened by the electrons in the inversion layer. Trapping of electrons in defect states positioned along the dominant current percolation paths will produce RTS with large amplitudes.

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Fig. 5. Potential distribution in three 50×50 nm MOSFETs with discrete random dopants in the channel region. The positional dependence of the magnitude of the RTS amplitudes associated with the trapping of a single electron is mapped in the plane above each transistor.

The potential distribution in three 50×50 nm MOSFETs with discrete random dopants in the channel region is presented in Fig. 5. The devices are selected from a sample of 200 transistors with randomly generated dopant distributions to have the smallest, the largest and a typical threshold voltage in the distribution. The plane above the channel of each transistor maps the RTS amplitudes associated with the trapping of a single electron at the interface. Unlike the continuous doping simulations, the largest RTS amplitudes in this case are not in the middle of the channel but in the regions with the deepest valley in the potential landscape corresponding to the highest density of percolating current.

Oxide thickness fluctuations

The gate dielectric thickness in mass production MOSFETs has already reached the 1.5 nm barrier with sub 1 nm physical thickness utilised in the advanced research devices. Atomic scale roughness of the Si/SiO₂ and gate/SiO₂ interfaces introduces significant intrinsic parameter fluctuations. Indeed when the oxide thickness is only a few silicon atomic layers the atomic scale interface roughness steps will result in significant oxide thickness variations (OTV) within the gate region of an individual MOSFET (see for reference Fig. 2). The unique random pattern of the gate oxide thickness and interface landscape makes each decananometre MOSFET different from its counterparts and leads to variations in the surface roughness limited mobility, gate tunnelling current and real or apparent threshold voltage from device to device.

In the same way as in the simulation of random dopant fluctuation effects, the numerical study of local oxide thickness fluctuation effects requires 3D statistical simulations of ensembles of MOSFETs with macroscopically identical design parameters but with microscopically different oxide thickness and interface patterns. It is also important to include quantum mechanical confinement effects, which push the inversion layer away from the rough interface and smooth the spatial inversion charge variations compared to classical simulations.

The random 2D surfaces used to represent the boundary between the oxide and the silicon and/or between the oxide and the gate material are constructed using standard assumptions for the autocorrelation function of the interface roughness. Generally, the interface is described by a Gaussian or exponential autocorrelation function with a given correlation length Λ and rms height Δ. There is reasonably close agreement in the rms values Δ of the interface roughness reported by different sources but the reported values for the correlation length Λ vary by more than an order of magnitude. Correlation lengths in the range of 1-3 nm are reported from TEM measurements and are typically used in Monte Carlo simulations and to fit surface roughness limited mobility to experimental data. At the same time the values of Λ reported from AFM measurements vary from 10-30 nm. Random 2D surfaces are generated from the corresponding power spectra using a standard 2D Fourier synthesis approach. The ‘analogue’ random surface is then quantised in steps to take into account the discrete nature of the interface roughness steps associated with the atomic layers in the crystalline silicon substrate. The step height is approximately 0.3 nm for the (001) interface.

A typical random Si-SiO₂ interface, generated according to the above described procedure and used in the simulation of a 30×30 nm MOSFET with average oxide thickness <t_ox> = 1.05 nm and continuous channel doping concentration N_A = 5×10¹⁸cm^-3 is shown at the top of Fig. 6. The interface has been reconstructed using the power spectrum for a Gaussian autocorrelation function. Only the roughness of the Si/SiO₂ interface was introduced in the simulations and the gate-SiO₂ interface was flat. The potential distribution at threshold voltage is shown at the bottom of the same figure. The oxide thickness fluctuations introduce surface potential fluctuations similar to the fluctuations introduced by random impurities. Density gradient quantum corrections are included in the simulation. One equiconcentration surface corresponding to electron charge density 1×10¹⁷cm^-3 is plotted in the middle, illustrating the quantum confinement effects in both vertical and lateral directions.

Line edge roughness

The line edge roughness (LER) caused by tolerances inherent to materials and tools used in the lithography processes is yet another source of intrinsic parameter fluctuations which needs close attention. LER has caused little worry in the past since the critical dimensions of MOSFETs were orders of magnitude larger than the roughness. However, as the aggressive scaling continues into the decananometre regime, LER does not scale accordingly, becoming an increasingly larger fraction of the gate length. As shown in Fig. 7 the edge roughness remains typically on the order of 5 nm almost independently of the type of lithography used in production or research.

Fig. 7. LER found in advanced lithography processes by various labs and required by the SIA roadmap The inset shows LER found in sub-100 nm e-beam generated lines.	Fig. 8. Potential distribution at threshold in a well scaled 50×200 nm MOSFET with line edge roughness of the gate of 3Δ = 6 nm.

The LER in the simulations is specified by rms amplitude Δ and correlation length Λ. This allows both 3D and statistical aspects of LER to be naturally incorporated in a single simulation framework. The reconstruction of realistic gate edges is based on a 1D Fourier synthesis approach, similar to that used in the generation of the Si-SiO₂ interface. The potential distribution in a 50×200 nm MOSFET with continuous doping and LER is shown in Fig. 8 for Λ = 20 nm and LER with 3Δ = 6 nm.