Dr. Binjie Cheng
Device Modelling Group,
Department of Electronics and Electrical Engineering,
Glasgow, G12 8LT
U.K.
Tel.
+44 141 3304792
Fax:
+44 141 3304907
E-mail:
b.cheng@elec.gla.ac.uk
Brief Biography
| Publications
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I
was born in
I was awarded
B.S., M.S. and Ph.D. degrees in Electronic Engineering by Xi’an
Jiaotong University, P. R. China, in 1994, 1997
and
2000 respectively. My Ph.D. dissertation title is: Study
on the modeling of Deep-Submicrometer Fully-Depleted SOI MOSFET’s
and the Extraction of Model Parameters.
After
attaining Ph. D. degree, I spent two years (10/2000-10/2002) as a
post-doctoral
researcher at the Cavendish
Laboratory, Cambridge
University. Since
October 2002, I've been a member of the Device Modelling Group, University
of Glasgow.
Since 1995, I
have worked on a wide range of research fields, including:
¨
Electron beam lithography
system
design, electromagnetic field simulation,
¨
Experimental study on e-e
interaction, process study on nanotip fabrication;
¨
Compact modelling of FD
MOSFET,
parameter extraction software based on Automatic Differential (AD);
¨
Intrinsic parameter
fluctuations
in devices and circuits at decananometer regime.
Currently, my
research is focused on the impact of intrinsic parameter fluctuation
(introduced by discrete random dopants, atomic scale oxide thickness
variation,
line edge roughness, material composition and strain variation) on
nanoCMOS circuits. I'm developing statistic compact modelling and
statistical
circuit simulation methodologies which can efficiently simulate the
effects of
intrinsic parameter fluctuation on yield and performance of circuit.
I'm also
interested in the fluctuation resistant design technologies.
I have more than 20 publications, have given presentations at various international conferences.
©
Binjie Cheng <b.cheng@elec.gla.ac.uk>
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